1. Field of the Invention
This invention relates generally to digital signal filter processing (DSP) and, particularly, relates to an apparatus and method for implementing digital interpolation and decimation having an improved finite impulse response (FIR) filter structure with time-varying coefficients.
2. Description of the Related Art
Digital television, video telecommunication devices, and personal computers often require resizing of image data through sampling rate conversion. Sampling rate conversion by a fractional amount(U/D), may be construed as increasing the sampling frequency by an integer factor U (also known as interpolation) and subsequently decreasing the sampling frequency by an integer factor D (also known as decimation). Given two-dimensional data, interpolation and decimation requires buffering rows of data, in order to access vertically adjacent samples not stored in contiguous memory locations. Interpolation, useful for raster imaging, requires large amounts of computer memory to store data in compressed form and to enlarge this data for display due to the buffering of input data. Likewise, prior art digital resampling techniques using decimation often require large amounts of computer memory to store digital input samples.
Thus, buffering input data imposes a high cost and size penalty on manufacturers of low-end, compact devices with small displays. Conversely, not buffering the output imposes a high cost on performance speed in high-end, wide-screen displays, requiring optimum speed rather than lower buffering requirements.
Some prior art digital signal processors use FIR filter structures with time-varying coefficients to enlarge and reduce the received image. Proakis and Manolakis describe such digital resampling techniques in xe2x80x9cIntroduction to Digital Signal Processing,xe2x80x9d pages 654-671 (1988). These FIR structures, operating at the output rate, compute each output sample as a linear combination of each input sample. The weight of each input sample varies according to its proximity to the output sample. When an image is interpolated by a large factor, the digital signal processor requires a high processing clock rate to interface with the incoming data stream. As a result, there exists an increase in hardware and, thus, cost.
During sampling rate enlargement, the output rate is relatively high, increasing the probability of a processing bottleneck. During sampling rate reduction, the amount of memory required to buffer the input can be excessive, increasing the cost and size of the apparatus. Therefore, the FIR filter implementation is complex in design and expensive.
Crochiere et al. describe a prior art single-stage interpolator-decimator circuit in U.S. Pat. No. 4,020,332 entitled INTERPOLATION-DECIMATION CIRCUIT FOR INCREASING OR DECREASING DIGITAL SAMPLING FREQUENCY, which is hereby incorporated by reference. Although Crochiere et al. has demonstrated that single stage or multistage interpolation and decimation result in computational efficiency, this prior art has not provided an interpolation or decimation circuit that can be realized by a simple circuit structure.
There is therefore a need for a fast, cost effective, computationally efficient method and apparatus for reducing and enlarging images by a fractional amount. It is also desirable that the method produces output images of as good or better quality than those produced using other known scaling techniques. Finally, such methods should be easily and conveniently implemented in hardware.
An improved FIR filter structure has time-varying coefficients for converting the sampling rate of a digital input signal by a fractional amount that eliminates input signal sample buffering and, thereby, reduces hardware requirements during a decimation operation and relieves the processing bottleneck during an interpolation operation, increasing the speed of the device.
The filter design includes a multiplier, a memory, a sequencer, an accumulator, and an output buffer. The multiplier having first and second input terminals for supplying an output signal that is the product of the signals applied to the first and second input terminal is coupled to the memory that stores L sets of coefficients gi(n). The sequencer for sequentially transferring each coefficient set gi(n) to the first multiplier input terminal and the input signal to the second multiplier input terminal is coupled to the multiplier and the memory. The accumulator for determining the output sample y(n) by summing the products supplied by multiplier over the range j=0 to j=Nxe2x88x921 is coupled to the sequencer. The output buffer is coupled to the accumulator for storing the accumulated output sample y(n).
The proposed structure, as shown in FIG. 3, operates at the input data rate and requires buffering of the output data. The filtering apparatus distributes the multi-bit digital input signal among the affected output samples, multiplying each input sample by the associated coefficients. The multiplier output is accumulated, forming partial sums to derive an associated output sample, rather than computing a weighted sum at the output data rate for each output sample as in the conventional FIR filtering scheme. Thus, buffering the output significantly reduces hardware and memory requirements during a decimation operation. Likewise, during interpolation of an image for a given multiplier speed, the speed of the apparatus increases, in light of a marginal increase in hardware requirement. FIG. 5 is a physical implementation of FIG. 3.